1. Field of the Present Invention
The present invention generally relates to the field of electronic devices and more particularly to the design of a clock generator circuit for use in a data processing system that generates an oscillating signal based on the capacitance of the clock driven logic on the system.
2. History of Related Art
In the field of electronic devices, clock signals and clock .generation circuits are well known. Conventional clock generators can be divided into two broad classes, generators for use in VLSI devices such as general purpose microprocessors and digital signal processors and generators for use in consumer electronic devices such as cell phones. Referring to FIG. 1, an exemplary VLSI-type generator 104 is shown as part of a VLSI device 101. VLSI device 101 comprises a single device fabricated on a monolithic substrate such as a silicon substrate. Device 101 includes a clock generator circuit 104, buffering circuitry 106, and functional logic collectively identified as load 110. VLSI device 101 typically receives an input from an external clock device 102 such as a crystal. Device 101 includes some form of clock generation circuit 104 such as a phase-locked loop or delay-locked loop that attempts to minimize the variation in frequency and/or phase in the on-chip clock. The output of the clock generator 104 is then typically amplified or buffered by buffering circuitry 106. The output of buffering circuitry 106 drives the functional logic (load 110) of device 101.
Referring to FIG. 2, an exponential horn implementation of buffering circuit 106 is shown. In this depiction, buffering circuitry 106 includes a series of conventional CMOS inverters 120. The size (measured as the ratio of the transistor""s width to length (W/L)) of each successive inverter is some geometric factor larger than the size of the preceding inverter.
Historically, the frequency of the clock signal provided to load 110 has been in the tens to hundreds of megahertz range. At such frequencies, the stray capacitance associated with load 110 is not sufficient to alter the shape of the clock signal significantly and the clock signal is therefore substantially square. Square wave signals are generally desirable as clocking signals in CMOS devices because the rapidity with which such signals transition between states beneficially reduces the CMOS crossover current and minimizes problems associated with intra-device variations in threshold voltage.
As circuits have advanced, however, it has become increasing problematic to generate square wave clock signals. The high frequency components required to generate good square waves are drastically attenuated by the stray capacitance associated with any semiconductor device. Manufacturers have been generally more successful in increasing the clocking frequency than they have been in reducing stray capacitance with the result being that it is increasingly difficult to generate square waves. This problem has motivated designers to consider the effects of a clock signal having rise and fall times that are relatively slow compared to a square wave.
Consumer electronic circuits, on the other hand, have typically implemented simpler and lower cost clock generators. These circuits most commonly incorporate some form of tank circuit in which an LC combination produces a substantially sinusoidal signal. This signal is buffered up and provided to the device""s functional circuitry.
While VLSI clock generators are generally superior to consumer electronic signal generators in terms of quality and tuning range, they require an external clock signal and tend to consume an undesirable amount of power in the buffering circuitry. While consumer product clock circuits have the advantage of being inexpensive, they have generally been unsuitable for VLSI devices because of the slow rise times and because, at historical clock frequencies, it has been impractical to design inductors and capacitors of sufficient size. (The characteristic frequency of an LC circuit is inversely proportional to the root of the LC product).
It would be desirable to implement a clock generation circuit for a VLSI device that incorporated the advantages of the consumer product clock generators without unduly comprising the quality of the clock signal and without producing a die size that is impractical.
The problems identified above are in large part addressed by a system and integrated circuit (die) including a clock generator in which an on-chip inductive element is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that is suitable for driving or clocking at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET""s, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET""s. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator""s inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.